Various schemes have been devised for error detection and correction in digital apparatus and devices such as memories. In the realm of error correction in memory devices, error detecting and error correcting may be performed separately. For example, schemes such as single error correcting-double error detecting (SEC-DED) have been devised which would allow for the correction of a single-bit error if a double-bit error is detected. In case of multiple-bit errors, however, conventional SEC-DED schemes may not be sufficiently powerful to mitigate these errors.
More powerful error detecting and correcting schemes have been devised to address the problem of multiple-bit errors. For example, schemes such as double error correcting-triple error detecting (DEC-TED) have been devised which would provide more powerful error correcting capabilities than conventional SEC-DED schemes. The area of circuitry typically required for DEC-TED, however, would be much larger than the area required for SEC-DED. Moreover, conventional DEC-TED circuitry typically consumes more power and results in longer latency or time delay than conventional SEC-DED circuitry. For example, when DEC-TED circuitry is utilized to correct a single error, power consumption and time delay would be much greater than SEC-DED circuitry.
Furthermore, pure combinational circuits implementing error correcting codes for single- or multiple-bit error correction may typically consume large amounts of dynamic power when the input changes due to invalid transitions in error location decoding. It would be desirable to reduce the amount of power consumption required for error detection and correction, especially for multiple-bit error detection and correction in low-power integrated circuit devices such as low-power memory chips.